Adjustable delay circuits have numerous applications and are used in particular when the phase between two logical signals is to be adjusted. In that case, the first of these signals is applied to the input of a delay circuit, and measuring the phase displacement between the output signal and the input signal is used to control the adjustment of the delay circuit.
Automatic phase control can be done by means of an analog or digital adjusting signal; the digital version is often preferred, because it is less sensitive to interference and to the attenuation involved in signal transmission. Moreover, when it is embodied as an integrated circuit, it is less sensitive to production variations.
A first known way to achieve a digitally controlled delay circuit consists in using a plurality of elementary gates, for example of the inverter type, associated with a digitally controlled interconnection system and enabling the cascade connection of a variable number of elementary gates. However, this type of circuit is limited to being employed in cases that do not require precision adjustment of any delay shorter than the intrinsic delay of the elementary gate.
Another known solution is to use a circuit of the resistor-capacitor type, where the resistor is constituted by a plurality of elementary resistors connected selectively in parallel as a function of the digital control. In that case, the delay is defined by the time constant of the circuit. If all the elementary resistors have the same resistance, then the delay obtained is inversely proportional to the number of resistors selected. To obtain a constant adjustment precision over the entire adjustment range, it is necessary for the function linking the delay to the digital adjustment variable to be as nearly as possible a linear function. The response obtained by the above solution is accordingly very far from a linear relationship. To approach such linearity, the elementary resistors must be dimensioned for quite precise resistances that are are all different from one another. This outcome is very difficult to obtain in the case of an integrated version, however. Moreover, it would be necessary to provide one such circuit for each signal that is to be adjusted.
For example, if the delay circuit is intended to be used in a phase-locked loop of the type described in European Patent Application published under No. 441 684, filed Jan. 30, 1991, and entitled "Circuit verrouille en phase et multiplieur de frequence en resultant" (PHASE-LOCKED LOOP AND RESULTANT FREQUENCY MULTIPLIER), corresponding to U.S. application Ser. No. 07/762,018, filed Sep. 18, 1991, in the name of Roland Marbot and assigned to the assignee of the present invention, then the foregoing solution is not satisfactory, because of its bulk and its sensitivity to production variations.
A method consisting in performing a superposition with weighting and an integral effect of the input signal and a signal delayed by a fixed value with respect to the input signal enables precise adjustment, with the possibility of obtaining a minimum delay shorter than the intrinsic delay of the elementary gates for the technology chosen. By limiting the value of the fixed delay, this solution also assures a linear response, with a good approximation, of the delay as a function of the digital command. The range of adjustment of the delay is then equal to the value of the fixed delay. For certain applications, it is desirable to be capable of adjusting the delay over a wide range. However, if the value of the fixed delay is increased beyond a certain value depending on the dimensions of the combination circuit, then the response of the delay as a function of the digital command becomes less and less linear, and finally has a discontinuity.